DR. GIRISH H; SHYLAJA V; DR. VIJAYALAKSHMI D; VANISHREE M L; SOUMYA N G; DR. ANITA P. Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics. Educational Administration: Theory and Practice, [S. l.], v. 30, n. 5, p. 12904–12909, 2024. DOI: 10.53555/kuey.v30i5.4465. Disponível em: https://kuey.net/index.php/kuey/article/view/4465. Acesso em: 30 sep. 2025.