YASHWANT ADITYA; PUSHPANJALI PANDEY; LEILA RZAYEVA. Enhancing DES Encryption Efficiency on 16 nm FPGA through Clock Gating for Low Power Design. Educational Administration: Theory and Practice, [S. l.], v. 30, n. 5, p. 10302–10309, 2024. DOI: 10.53555/kuey.v30i5.4741. Disponível em: https://kuey.net/index.php/kuey/article/view/4741. Acesso em: 17 sep. 2025.