Yashwant Aditya, Pushpanjali Pandey, and Leila Rzayeva. 2024. “Enhancing DES Encryption Efficiency on 16 Nm FPGA through Clock Gating for Low Power Design”. Educational Administration: Theory and Practice 30 (5):10302-9. https://doi.org/10.53555/kuey.v30i5.4741.