Dr. Girish H, Shylaja V, Dr. Vijayalakshmi D, Vanishree M L, Soumya N G, and Dr. Anita P. “Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics”. Educational Administration: Theory and Practice 30, no. 5 (May 31, 2024): 12904–12909. Accessed September 30, 2025. https://kuey.net/index.php/kuey/article/view/4465.