Dr. Girish H, Shylaja V, Dr. Vijayalakshmi D, Vanishree M L, Soumya N G, Dr. Anita P. Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics. kuey [Internet]. 2024 May 31 [cited 2025 Sep. 30];30(5):12904-9. Available from: https://kuey.net/index.php/kuey/article/view/4465