Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

Abstract

Introduction: This paper proposes two new reverse converters for balanced and well-formed five-moduli set {2ⁿ+1, 2^n-1-1, 2ⁿ, 2ⁿ⁺¹-1, 2ⁿ-1}. The converters are planned in a two-level architecture while appreciating adder base structures without utilizing any ROM, which results in an efficient implementation in VLSI circuits.

Materials and Methods: To design both levels of the proposed reverse converters, Mixed-Radix Conversation (MRC) algorithm is employed.

Results and Discussion:  Unit gate delay and area estimation demonstrate the proposed reverse converter (DC1) is faster than other alternatives, the similar five moduli reverse converter, under distinctive dynamic ranges while the second design (DC2) requires less hardware cost.

Conclusion: The synthesis results on Xilinx Virtex-7 FPGA illustrate that, comparing to the latest five moduli set reverse converters, the proposed converter (DC1) has achieved 11%, 12% and 11% improvement in speed for n = 12, 16 and 20, respectively.