Enhancing DES Encryption Efficiency on 16 nm FPGA through Clock Gating for Low Power Design

Abstract

As advancement in the tech world is rapidly increasing, data privacy and message privacy are becoming crucial in today’s generation. Securing the data with the hardware mechanism is in great demand. In this research work, a secure mechanism of hardware implementation is being highlighted. To secure the message, a Data Encryption Standard (DES) algorithm is implemented on a Field Programmable Gate Array (FPGA) device. The algorithm is implemented on a Kintex Ultrascale + 16 nm device, and the results are tested for five different ranges (1ns-25ns) of clock cycles to make the hardware design power-efficient. The encryption process utilizes low power at 25 ns clock cycle, as there is a decrement in the clock cycle speed for the encryption process the power consumption gets increased.