Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics

Abstract

A Vedic multiplier architecture is employed in constructing a 32-bit RISC-V processor to enhance speed and reduce computational complexity. It’s ALU and MAC units, based on Vedic Sutras, are implemented in Verilog HDL and simulated with the Xilinx design suite, achieving lower power consumption and latency compared to traditional designs. The processor includes conventional components like the Control Unit, Register Bank, Program Counter, and Memory. It can execute up to 16 instructions, making it a powerful option for various computing tasks due to its improved speed, reduced power consumption, and minimized area usage.